Metal-Oxide-Semiconductor field effect transistor (MOSFET) technology is the dominant electronic device technology in use today. Performance enhancement between generations of devices is generally achieved by reducing the size of the device, resulting in an enhancement in device speed. This is generally referred to as device “scaling”.
Ultra-large-scale integrated (ULSI) circuits generally include a multitude of transistors, such as more than one million transistors and even several million transistors that cooperate to perform various functions for an electronic component. The transistors are generally complementary metal oxide semiconductor field effect transistors (CMOSFETs) which include a gate conductor disposed between a source region and a drain region. The gate conductor is provided over a thin gate oxide material. Generally, the gate conductor can be a metal, a polysilicon, or polysilicon/germanium (SixGe(1-x) material that controls charge carriers in a channel region between the drain and the source to turn the transistor on and off. The transistors can be N-channel MOSFETs or P-channel MOSFETs.
In bulk semiconductor-type devices, transistors such as MOSFETs, are built on the top surface of a bulk substrate. The substrate is doped to form source and drain regions, and a conductive layer is provided between the source and drain regions. The conductive layer operates as a gate for the transistor; the gate controls current in a channel between the source and the drain regions. As transistors become smaller, the body thickness of the transistor (or thickness of depletion layer below the inversion channel) must be scaled down to achieve superior short-channel performance.
As MOSFETs are scaled to channel lengths below 100 nm, conventional MOSFETs suffer from several problems. In particular, interactions between the source and drain of the MOSFET degrade the ability of the gate to control whether the device is on or off. This phenomenon is called the “short-channel effect”.
Silicon-on-insulator (SOI) MOSFETs are formed with an insulator (usually, but not limited to, silicon dioxide) below the device active region, unlike conventional “bulk” MOSFETs, which are formed directly on silicon substrates, and hence have silicon below the active region.
Conventional SOI-type devices include an insulative substrate attached to a thin-film semiconductor substrate that contains transistors similar to the MOSFETs described with respect to bulk semiconductor-type devices. The insulative substrate generally includes a buried insulative layer above a lower semiconductor base layer. The transistors on the insulative substrate have superior performance characteristics due to the thin-film nature of the semiconductor substrate and the insulative properties of the buried insulative layer. In a fully depleted (FD) MOSFET, the body thickness is so small that the depletion region has a limited vertical extension, thereby eliminating link effect and lowering hot carrier degradation. The superior performance of SOI devices is manifested in superior short-channel performance (i.e., resistance to process variations in small size transistors), near-ideal subthreshold voltage swing (i.e., good for low off-state current leakage), and high saturation current. SOI is advantageous since it reduces unwanted coupling between the source and the drain of the MOSFET through the region below the channel. This is often achieved by ensuring that all the silicon in the MOSFET channel region can be either inverted or depleted by the gate (called a fully depleted SOI MOSFET). As device size is scaled, however, this become increasingly difficult, since the distance between the source and drain is reduced, and hence, they increasingly interact with the channel, reducing gate control and increasing short channel effects (SCE). The double-gate MOSFET structure is promising since it places a second gate in the device, such that there is a gate on either side of the channel. This allows gate control of the channel from both sides, reducing SCE. Additionally, when the device is turned on using both gates, two conduction (“inversion”) layers are formed, allowing for more current flow. An extension of the double-gate concept is the “surround-gate” or “wraparound-gate” concept, where the gate is placed such that it completely or almost-completely surrounds the channel, providing between gate control.
In a double gate field effect transistor (FinFET), the device channel comprises a thin silicon fin standing on an insulative layer (e.g. silicon oxide) with the gate in contact with the sites of the fin. Thus inversion layers are formed on the sides of the channel with the channel film being sufficiently thin such that the two gates control the entire channel film and limit modulation of channel conductivity by the source and drain.
The double gates on the channel fin effectively suppress SCE and enhance drive current. Further, since the fins is thin, doping of the fin is not required to suppress SCE and undoped silicon can be used as the device channel, thereby reducing mobility degradation due to impurity scattering. Further, threshold voltage of the device may be controlled by adjusting the work function of the gate by using a silicon-germanium alloy or a refractory metal or its compound such as titanium nitride.
Generally, it is desirable to manufacture smaller transistors to increase the component density on an integrated circuit. It is also desirable to reduce the size of integrated circuit structures, such as vias, conductive lines, capacitors, resistors, isolation structures, contacts, interconnects, etc. For example, manufacturing a transistor having a reduced gate length (a reduced width of the gate conductor) can have significant benefits. Gate conductors with reduced widths can be formed more closely together, thereby increasing the transistor density on the IC. Further, gate conductors with reduced widths allow smaller transistors to be designed, thereby increasing speed and reducing power requirements for the transistors.
Heretofore, lithographic tools are utilized to form transistors and other structures on the integrated circuit. For example, lithographic tools can be utilized to define gate conductors, active lines conductive lines, vias, doped regions, and other structures associated with an integrated circuit. Most conventional lithographic fabrication processes have only been able to define structures or regions having a dimensions of 100 nm or greater.
In one type of conventional lithographic fabrication process, a photoresist mask is coated over a substrate or a layer above the substrate. The photoresist mask is lithographically patterned by providing electromagnetic radiation, such as ultraviolet light, through an overlay mask. The portions of the photoresist mask exposed to the electromagnetic radiation react (e.g. are cured). The uncured portions of the photoresist mask are removed, thereby transposing the pattern associated with the overlay to the photoresist mask. The patterned photoresist mask is utilized to etch other mask layers or structures. The etched mask layer and structures, in turn, can be used to define doping regions, other structures, vias, lines, etc.
As the dimensions of structures or features on the integrated circuit reach levels below 100 nm or 50 nm, lithographic techniques are unable to precisely and accurately defined the feature. For example, as described above, reduction of the width of the gate conductor (the gate length) associated with a transistor or of the active lines associated with an SOI transistor has significant beneficial effects. Future designs of transistors may require that the active lines have a width of less than 50 nanometers.
Double gate SOI MOSFETs have received significant attention because of its advantages related to high drive current and high immunity to short channel effects. The double-gate MOSFET as able to increase the drive current because the gate surrounds the active region by more than one layer (e.g., the effective gate total width is increased due to the double gate structure). However, patterning narrow, dense active regions is challenging. As discussed above with respect to gate conductors, conventional lithographic tools are unable to accurately and precisely define active regions as structures or features with dimensions below 100 nm or 50 nm.
Thus, there is a need for an integrated circuit or electronic device that includes smaller, more densely disposed active regions or active lines. Further still, there is a need for a ULSI circuit which does not utilize conventional lithographic techniques to define active regions or active lines.
Even further still, there is a need for a non-lithographic approach for defining active regions or active lines having at least one topographic dimension less than 100 nanometers and less than 50 nanometers (e.g., 20-50 nm). Yet further still, there is a need for an SOI integrated circuit with transistors having multiple sided gate conductors associated with active lines having a width of about 20 to 50 nm.
The present invention is directed to a process for fabricating FinFET transistor structures which is an extension of conventional planar MOSFET technology and resulting structures.